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SUMMARY:Development of the ATLAS Liquid Argon Calorimeter Readout    Elect
 ronics for the HL-LHC
DTSTART;VALUE=DATE-TIME:20230907T140000Z
DTEND;VALUE=DATE-TIME:20230907T142000Z
DTSTAMP;VALUE=DATE-TIME:20260717T044001Z
UID:indico-contribution-3197@indico.tlabs.ac.za
DESCRIPTION:Speakers: Arno Straessner (Technische Universität Dresden)\nA
  new era of hadron collisions will start around 2029 with the\n   High-Lum
 inosity LHC which will allow to collect ten times more data\n   than what 
 has been collected during 10 years of operation at LHC.\n   This will be a
 chieved by higher instantaneous luminosity at the\n   price of a higher nu
 mber of collisions per bunch crossing.\n\n   In order to withstand the hig
 h expected radiation doses and the harsher\n   data taking conditions\, th
 e ATLAS Liquid Argon Calorimeter readout\n   electronics will be upgraded.
 \n\n   The electronic readout chain is composed of four main components.\n
    1: New front-end boards will allow to amplify\, shape and digitise the\
 n      calorimeter’s ionisation signal on two gains over a dynamic range
  of\n      16 bits and 11 bit precision. Low noise below Minimum Ionising\
 n      Particle (MIP)\, i.e. below 120 nA for 45 ns peaking time\, and max
 imum\n      non-linearity of two per mille is required. Custom preamplifie
 rs and\n      shapers are being developed to meet these requirements using
  65 nm and\n      130 nm CMOS technologies. They shall be stable under irr
 adiation until\n      1.4kGy (TID) and 4.1x10^13 new/cm^2 (NIEL). Two conc
 urrent preamp-shaper\n      ASICs were developed and\, “ALFE”\, the be
 st one has been chosen. The test\n      results of the latest version of t
 his ASIC will be presented. “COLUTA”\,\n      a new ADC chip is also b
 eing designed. A production test setup is being\n      prepared and integr
 ation tests of the different components (including\n      lpGBT links deve
 loped by CERN) on a 32-channels front-end board are\n      ongoing\, and r
 esults of this integration will be shown.\n   2: New calibration boards wi
 ll allow the precise calibration of all\n      182468 channels of the calo
 rimeter over a 16 bits dynamic range. A\n      non-linearity of one per mi
 lle and non-uniformity between channels of\n      0.25% with a pulse rise 
 time smaller than 1ns shall be achieved. In\n      addition\, the custom c
 alibration ASICs shall be stable under\n      irradiation with same levels
  as preamp-shaper and ADC chips. The HV\n      SOI CMOS XFAB 180nm technol
 ogy is used for the pulser ASIC\, “CLAROC”\,\n      while the TSMC 130
  nm technology is used for the DAC part\, “LADOC”.\n      The latest v
 ersions of those 2 ASICs which recently passed the production\n      readi
 ness review (PDR) with their respective performances will be presented.\n 
   3: New ATCA compliant signal processing boards (“LASP”) will receive
 \n      the detector data at 40 MHz where FPGAs connected through lpGBT\n 
      high-speed links will perform energy and time reconstruction. In\n   
    total\, the off-detector electronics receive 345 Tbps of data via 33000
 \n      links at 10 Gbps. For the first time\, online machine learning tec
 hniques\n      are considered to be used in these FPGAs. A subset of the o
 riginal data\n      is sent with low latency to the hardware trigger syste
 m\, while the\n      full data are buffered until the reception of trigger
  accept signals. The\n      latest development status of the board as well
  as the firmware will\n      be shown.\n   4: A new timing and control sys
 tem\, “LATS”\, will synchronise with the\n      aforementioned compone
 nts. Its current design status will also be\n      shown.\n\nhttps://indic
 o.tlabs.ac.za/event/112/contributions/3197/
LOCATION: Meeting Room 2.44 - 2.46
URL:https://indico.tlabs.ac.za/event/112/contributions/3197/
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