RAM Benchmarking performance for ARM Processors

Not scheduled
HUB 211 (University of the Witwatersrand)

HUB 211

University of the Witwatersrand

Wits Professional Development HUB 92 Empire Road, Braamfontein 2001, Johannesburg

Speaker

Mr Robert Reed (University of the Witwatersrand)

Description

The Large Hadron Collider (LHC) at CERN is currently undergoing a major upgrade to handle higher energies. This will be the first of two upgrades and the expected amount of data produced by this upgraded system will far exceed current data throughput capabilities. It is expected that the same will be so for the Square Kilometre Array (SKA) Radio Telescope. A potential alternative to current high performance computing systems involves using low-cost, low-power ARM processors in large arrays to provide massive parallelisation and hence large data throughput. As memory performance will play an important role in high-throughput computing, several tests and applications such as the STREAM benchmark have been used to thoroughly evaluate and benchmark the memory (RAM) performance of three different models of ARM processor, namely the Cortex-A7, Cortex-A9, and Cortex-A15. Various aspects of memory performance have been evaluated, including the effects of using multiple processors in a cluster-configuration.

Summary

Keywords: ARM, memory, RAM, benchmark, high-throughput computing, high-performance
computing, LHC, ATLAS, SKA, CERN.

Primary authors

Mr Gerhard Harmsen (University of the Witwatersrand) Mr Robert Reed (University of the Witwatersrand) Mr Thomas Wrigley (University of the Witwatersrand)

Presentation Materials

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