High-performance Signal and Data Processing: Challenges in Astro- and Particle Physics and Radio Astronomy Instrumentation

A Scalable Heterogeneous Architecture for Software Defined Radio on the RHINO platform

Not scheduled

HUB 211 (University of the Witwatersrand)

Speaker

Mr Matthew Bridges (University of Cape Town)

Description

Since the adoption of Software Defined Radio (SDR) into the fields of Wireless Communications, RADAR and Radio Astronomy there has been an ever-growing need for high performance computer systems optimised for large bandwidth Digital Signal Processing. Some of the key factors which affect the performance throughput of these systems are: 1. The number of processing elements 2. Processing frequency 3. Memory access latency 4. External Interfacing (Ease of and data throughput) 5. Ease of programming FPGAs perform very well as a SDR platform due to their reconfigurable and highly parallel nature as well as simple, high-throughput external interfacing. However, FPGAs are renowned for being very difficult platforms to program and the designs created for them are often fixed after compile time and are not interactive. At the other end of the scale microprocessor are integrated circuits designed to perform general purpose computation and are therefore very versatile and interactive. However, their fixed data path and limited parallelism makes them ineffective for many applications including SDR. The Reconfigurable Hardware Interface for computiNg and radiO (RHINO) Board is an open-source platform developed at the University of Cape Town for the purpose of SDR and computation. It's main processing element is a large Xilinx Spartan 6 FPGA which is coupled to an ARM microcontroller from Texas Instruments. The board also has high speed networking and Input/Output interfaces as well as a large amount of memory. The aim of this research was to build a framework for simplifying the development of interactive and parameterized logic cores. On the RHINO, these logic cores are then memory mapped to the processor creating a heterogeneous system. An architecture capable of performing the tasks of an SDR Transceiver was then developed from logic cores created using this framework and serves as the starting point for SDR on the RHINO allowing more complicated systems to be built on top. Although this project was focused on Software Defined Radio, the framework was designed for general computation and is therefore applicable to other fields which require complicated computation.