Speaker
Description
A new era of hadron collisions will start around 2029 with the
High-Luminosity LHC which will allow to collect ten times more data
than what has been collected during 10 years of operation at LHC.
This will be achieved by higher instantaneous luminosity at the
price of a higher number of collisions per bunch crossing.
In order to withstand the high expected radiation doses and the harsher
data taking conditions, the ATLAS Liquid Argon Calorimeter readout
electronics will be upgraded.
The electronic readout chain is composed of four main components.
1: New front-end boards will allow to amplify, shape and digitise the
calorimeter’s ionisation signal on two gains over a dynamic range of
16 bits and 11 bit precision. Low noise below Minimum Ionising
Particle (MIP), i.e. below 120 nA for 45 ns peaking time, and maximum
non-linearity of two per mille is required. Custom preamplifiers and
shapers are being developed to meet these requirements using 65 nm and
130 nm CMOS technologies. They shall be stable under irradiation until
1.4kGy (TID) and 4.1x10^13 new/cm^2 (NIEL). Two concurrent preamp-shaper
ASICs were developed and, “ALFE”, the best one has been chosen. The test
results of the latest version of this ASIC will be presented. “COLUTA”,
a new ADC chip is also being designed. A production test setup is being
prepared and integration tests of the different components (including
lpGBT links developed by CERN) on a 32-channels front-end board are
ongoing, and results of this integration will be shown.
2: New calibration boards will allow the precise calibration of all
182468 channels of the calorimeter over a 16 bits dynamic range. A
non-linearity of one per mille and non-uniformity between channels of
0.25% with a pulse rise time smaller than 1ns shall be achieved. In
addition, the custom calibration ASICs shall be stable under
irradiation with same levels as preamp-shaper and ADC chips. The HV
SOI CMOS XFAB 180nm technology is used for the pulser ASIC, “CLAROC”,
while the TSMC 130 nm technology is used for the DAC part, “LADOC”.
The latest versions of those 2 ASICs which recently passed the production
readiness review (PDR) with their respective performances will be presented.
3: New ATCA compliant signal processing boards (“LASP”) will receive
the detector data at 40 MHz where FPGAs connected through lpGBT
high-speed links will perform energy and time reconstruction. In
total, the off-detector electronics receive 345 Tbps of data via 33000
links at 10 Gbps. For the first time, online machine learning techniques
are considered to be used in these FPGAs. A subset of the original data
is sent with low latency to the hardware trigger system, while the
full data are buffered until the reception of trigger accept signals. The
latest development status of the board as well as the firmware will
be shown.
4: A new timing and control system, “LATS”, will synchronise with the
aforementioned components. Its current design status will also be
shown.
